1. Technical Field
Embodiments described herein are related to the field of memory implementation, and more particularly to techniques for data storage cell testing.
2. Description of the Related Art
Memories typically include a number of data storage cells composed of interconnected transistors fabricated on a semiconductor substrate. Such data storage cells may store a single data bit or multiple data bits and may be constructed according to a number of different circuit design styles. For example, the data storage cells may be implemented as a single transistor coupled to a capacitor to form a dynamic storage cell. Alternatively, cross-coupled inverters may be employed to form a static storage cell or a floating gate MOSFET may be used to create a non-volatile storage cell.
During the semiconductor manufacturing process, variations in lithography, transistor dopant levels, etc., may result in different electrical characteristics between transistors that are intended to have identical characteristics. Additional variation in electrical characteristics may occur due to aging effects within transistors as the device is repeatedly operated. These differences in electrical characteristics between transistors can result in data storage cells that output different small signal voltages for the same stored data. In a memory array, there may be a large variation in the small signal output voltages across the data storage cells that comprise the memory array.
Data from data storage cells that generate a smaller than average output signal due to the previously described variation may not be able to be read correctly, resulting in a misread. Data storage cells that fail to read properly may contribute to lower manufacturing yield and necessitate additional redundant data storage cells to maintain manufacturing yield goals.